Voltage controlled oscillators (VCOs) and phase lock loops (PLLs) are examples of clock generators that can produce digital clock signals for synchronous digital circuits. Digital clock signals, which are simply called clocks, can cause pattern noise or inter-symbol interference on digital lines if either the clock is imbalanced, the rise and fall times of the clock pulse edges are unequal, or both. Unbalanced clocks are clocks for which the duration of the high level signal is unequal to the duration of the low level signal. Balanced clocks have equal durations at both high and low levels, i.e., balanced clocks have 50% duty cycle.
Balanced clocks may be generated, for example, by taking a high frequency master clock that has a constant period and dividing by an integer. The integer is usually a power of two. Typically, generation of balanced divided clocks entails relatively complex analog circuit design and only a limited selection of output clock frequencies may be generated from any given master clock.
A clock divider formed of a standardized circuit block and which may be employed to generate multiple, balanced, phase-aligned, integer-divided output clocks is disclosed in the present assignee's co-pending U.S. patent application Ser. No. 11/876,526, “Apparatus and Method for Generating a Clock Signal,” filed Oct. 22, 2007, the disclosure of which is incorporated by reference in it's entirety.